1. Field of the Invention
The present invention relates to a phase-locked loop used in a frequency demodulator, and more specifically to such a loop designed to lock on a carrier frequency which can vary within a wide range.
2. Discussion of the Related Art
FIG. 1 schematically shows a conventional phase-locked loop capable of locking on a carrier frequency that varies within a wide range. This phase-locked loop includes a main phase-locked loop 10 and a locking aid circuit 12 which is conventionally formed of an auxiliary phase-locked loop.
Main phase-locked loop 10 includes a multiplier 14 receiving input signal Fin and the output of a (voltage or current) controlled oscillator 16. The output of multiplier 14 controls oscillator 16 via a low-pass filter 18 for eliminating the carrier frequency and passing the modulated frequencies. The output of filter 18 forms the demodulated signal Id.
Locking aid circuit 12 provides a d.c. presetting signal I0 that an adder 19 superposes to demodulated signal Id to set the quiescent frequency of oscillator 16 to the carrier frequency of signal Fin.
The auxiliary phase-locked loop of aid circuit 12 includes a multiplier 20 receiving input signal Fin and the output of a (current or voltage) controlled oscillator 22. The output of multiplier 20 is provided to the control input of oscillator 22 via a low-pass filter 24, the pass-band of which, much higher than that of filter 18, is adapted to the variation range of the carrier frequency of signal Fin.
The output of filter 24 forms signal I0 for presetting the quiescent frequency of oscillator 16 after a new filtering by a low-pass filter 26. The pass-band of filter 26 is such that signal I0 is a d.c. signal and corresponds to the mean value of the output signal of filter 24. In any case, the pass-band of filter 26 is lower than the lowest frequency of demodulated signal Id.
FIG. 2 schematically shows a conventional current-controlled oscillator, which can be used for oscillators 16 and 22. This oscillator includes a capacitor C, a terminal of which is connected to a fixed potential, such as ground GND. The other terminal of capacitor C is connected to the input of a Schmitt trigger or hysteresis comparator 30, to a charge current source 32 by a switch K1, and to a discharge current source 33 by a switch K2. Current sources 32 and 33 are further connected, respectively, to a high supply potential Vcc and to ground GND.
The output Vs of hysteresis comparator 30 directly controls switch K2 and controls switch K1 via an inverter 35.
The current of sources 32 and 33 is determined by a current Iin. Actually, sources 32 and 33 are formed of output branches of current mirrors, the input branches of which receive current Iin.
In operation, when output Vs is at zero, switch K1 is closed and capacitor C charges through source 32. When the high threshold of hysteresis comparator 30 is reached, output Vs switches. Then, switch K1 opens while switch K2 closes, causing the discharge of capacitor C through source 33. If the current of sources 32 and 33 varies, the charge and discharge times of the capacitor, and therefore the frequency of output signal Vs, also vary.
In the circuit of FIG. 1, presetting signal I0 is the d.c. component of the control signal of oscillator 22, and thus is the value which sets the quiescent frequency of oscillator 22 to the carrier frequency of signal Fin. In principle, if oscillators 16 and 22 are coupled and operate in the same conditions, signal I0 also sets the quiescent frequency of oscillator 16 to the carrier frequency of signal Fin.
The coupling is not difficult to obtain in integrated technology. However, oscillator 22 will never operate in the same conditions as oscillator 16. Indeed, the control signal of oscillator 22 exhibits significant frequency variations, due to the high pass-band of filter 24, while the control signal of oscillator 16 varies slowly. As a result, presetting signal I0 is not exactly the signal which should be applied to oscillator 16 to set its quiescent frequency to the carrier frequency of signal Fin.
This error of presetting signal I0 can cause losses of locking of loop 10, which causes a risk of capturing wrong frequencies in the qFin form present in the pass-band of filter 24 (q being a quotient of two integers).
Further, phase-locked loop 10 attempts to compensate this error of signal I0 by generating a d.c. component which superposes to output signal Id. This d.c. component must generally be suppressed downstream and decreases the dynamic range of the output signal.